These properties hold not only when XOR is applied to a single bit, but also when it is applied bitwise to a vector of bits e. We can interpret the action of XOR in a number of different ways, and this helps to shed light on its properties. The last, and most powerful, interpretation of XOR is in terms of parity , i.
This can be proved quite easily by induction and use of associativity. It is the crucial observation that leads to many of the properties that follow, including error detection, data protection and adding. Armed with these ideas, we are ready to explore some applications of XOR. Consider the following simple code snippet:.
This will toggle between two values x and y , alternately printing one and then the other. How does it work? To prove that this is the case we will use all of the properties covered earlier:.
Did you work it out? The second line comprises an expression that evaluates to a and stores it in b , just as the toggling example did. The third line comprises an expression that evaluates to b and stores it in a.
This is an example of aliasing , where two arguments to a function share the same location in memory, so altering one will affect the other. Perhaps there is some retribution for this much maligned idea, however. This is more than just a devious trick when we consider it in the context of assembly language. A node in a singly linked list contains a value and a pointer to the next node. A node in a doubly linked list contains the same, plus a pointer to the previous node. Note that the nodes at either end store the address of their neighbours.
Then the code to traverse the list looks like Listing 1, which was adapted from Stackoverflow [ Stackoverflow ]. This uses the same idea as before, that one state is the key to getting at the other. If we know the address of any consecutive pair of nodes, we can derive the address of their neighbours.
In particular, by starting from one end we can traverse the list in its entirety. A nice feature of this function is that this same code can be used to traverse either forwards or backwards. XOR can also be used to generate pseudorandom numbers in hardware. A pseudorandom number generator whether in hardware or software e. This can be achieved very fast in hardware using a linear feedback shift register.
To generate the next number in the sequence, XOR the highest 2 bits together and put the result into the lowest bit, shifting all the other bits up by one. This is a simple algorithm but more complex ones can be constructed using more XOR gates as a function of more than 2 of the lowest bits [ Yikes ]. By choosing the architecture carefully, one can construct it so that it passes through all possible states before returning to the start of the cycle again Figure 4.
The essence of encryption is to apply some key to an input message in order to output a new message. The encryption is only useful if it is very hard to reverse the process.
We can achieve this by applying our key over the message using XOR see Listing 2. The choice of key here is crucial to the strength of the encryption. If it is short, then the code could easily be cracked using the centuries-old technique of frequency analysis. As an extreme example, if the key is just 1 byte then all we have is a substitution cipher that consistently maps each letter of the alphabet to another one. This is known as a stream cipher , and in a real-worl situation this would also be combined with a secure hash function such as md5 or SHA Gate , however, still occupies a large area.
For each gate, either the Vdd line or Gnd line drives the output. When an input changes, the transistors that are conducting turn off to remove the conduction from the line currently driving the output. Other transistors, corresponding to the input transition, turn on to supply the conduction from the other line to drive the output. The transistors turning off, however, drain current from the output, thereby increasing delay. For both gates, the early part of the transition is wasted waiting for the gates of the turning on transistors to surpass the threshold.
This waiting reduces the performance of the circuits. In accordance with the present invention, a logic gate has been designed to optimize performance for situations where the order of inputs and which input will change first is known and transitions or events at the inputs alternate. The logic gate takes advantages of knowing the order of transitions to reduce the number of transistors and the amount of delay for XOR and XNOR gates.
In an apparatus according to the present invention, four transistors are arranged and coupled to produce logical outputs without Vdd or Gnd lines. The following description, as well as the practice of the invention, set forth and suggest additional advantages and purposes of this invention. The elements and combinations set forth in the claims achieve these advantages and purposes.
To obtain the advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a logic gate for producing an output logic signal representing a logical operation of a first logic signal and a second logic signal includes first, second, third, and fourth input terminals receiving, respectively, the first logic signal, the second logic signal, a first inverted logic signal representing the logical inverse of the first logic signal, and second inverted logic signal representing the logical inverse of the second logic signal; a non-inverting stage; an inverting stage; and an output terminal.
The non-inverting stage includes a first transistor of a first type having its channel coupled at a first end to the first input terminal and having its gate coupled to the fourth input terminal, and a second transistor of a second type, different from the first type, having its channel coupled between a second end of the channel of the first transistor and the second input terminal and having its gate coupled to the first input terminal. The inverting stage includes a third transistor of a first type having its channel coupled at a first end to the third input terminal and having its gate coupled to the second input terminal, and a fourth transistor of a second type having its channel coupled between a second end of the channel of the third transistor and the fourth input terminal and having its gate coupled to the third input terminal.
The output terminal is coupled to the junction of the channels of the first transistor and the second transistor and to the junction of the channels of the third transistor and fourth transistor to provide the output logic signal. Where the first and third transistors are N-type transistors, and the second and fourth transistors are P-type transistors, the output logic signal represents an exclusive OR operation of the first and second logic signals.
Where the first and third transistors are P-type transistors, and the second and fourth transistors are N-type transistors, the output logic signal represents an exclusive NOR operation of the first and second logic signals.
Both the foregoing general description and the following detailed description provide examples and explanations only. They do not restrict the claimed invention. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, explain the advantages and principles of the invention.
In the drawings,. Reference will now be made to various embodiments according to this invention, examples of which are shown in the accompanying drawings and will be obvious from the description of the invention. In the drawings, the same reference numbers represent the same or similar elements in the different drawings whenever possible.
This invention relates to a logic gate called an Inverse Toggle. A Toggle circuit, which relates to the Inverse Toggle as described more completely herein, has a single input and two outputs. A transition or event at the input causes a transition or event at one of the two outputs, and a subsequent event at the input causes an event at the other output.
All succeeding events at the input alternately cause events at the two outputs. The result is that events at the input of the Toggle cause events at the outputs to alternate in a known order.
The logic gate in accordance with the present invention, on the other hand, takes advantage of situations where the order of inputs to a circuit is known and the input events alternate. Designing a circuit to take advantage of known input behavior permits certain efficiencies and, in this invention, results in a faster circuit with fewer transistors than conventional XOR and XNOR circuits.
Several circuits, such as event control logic, have inputs that behave in this manner and thus can benefit from the Inverse Toggle. XOR gate includes a non-inverting stage and an inverting stage Non-inverting stage includes an N-type transistor and a P-type transistor , as well as input terminals and Similarly, inverting stage comprises an N-type transistor , a P-type transistor , and input terminals and XOR gate also includes an output terminal In non-inverting stage , terminal is coupled to one end of the channel of transistor , and terminal is coupled to its gate.
Transistor has its channel coupled between terminal and the other end of the channel of transistor , and has its gate coupled to terminal In inverting stage , terminal is coupled to one end of the channel of transistor , and terminal is coupled to its gate.
Transistor has its channel coupled between terminal and the other end of the channel of transistor , and its gate coupled to terminal Output terminal is coupled to both non-inverting stage and inverting stage In non-inverting stage , output terminal is coupled to the junction of the channels of transistors and Likewise, output terminal is coupled to the junction of the channels of transistors and of inverting stage Gate operates efficiently when signals A and B alternately change, representing perhaps alternating events, and Gate acts as an Inverse Toggle.
Initially, when both A and B are low logical 0 , the output for gate is low. When A becomes high, the output for gate becomes high. Gate derives its speed from the complementary nature of the N-type and P-type transistors.
Therefore, when conducting, N-type transistors pass a low signal and P-type transistors pass a high signal, and they both act as pass transistors. When fully conducting, a transistor acts as a pass transistor since a signal passes from one end of its channel to the other.
Applying the input logic signals shown in Fig. Initially, only N-type transistor is conducting because r- B is high and A and B are both low. N-type transistor does not conduct because its gate is low, and P-type transistor does not conduct because its gate is high. Transistor conducts a low logic signal to output terminal , indicating the appropriate false condition logical 0 because A and B are equal.
As A begins to change from a low to high state, output terminal draws current from the changing input A, driving terminal high through pass transistor which is still fully conducting. Because transistor is an N-type transistor, however, it cannot pull the output all the way high because that will begin to turn transistor off.
Midway through the transition, however, both transistors and are partially conducting. Because transistor conducts a high signal, partially conducting transistor also drives the output high.
Thus, the partially conducting transistors and are driving OUT in the same direction. Using input r-B to drive the output will make the input droop slightly, but still drive OUT fully high. Once fully conducting, transistor will become a pass transistor.
The improved speed of the circuit and its reduced delay come as a consequence of the combined effects of the transistor driving the output high during the initial part of the transition, and transistor driving OUT the rest of the way high during the latter part of the transition.
Both transistors drive the output in the same direction. In contrast, the conventional XOR circuit Fig. During a transition, the transistors enabling one line to drive the output e. Vdd turn off, while transistors enabling the other line to drive the output e.
Gnd turn on. Unlike the Inverse Toggle design of the present invention, however, the transistors turning off also drain current from the output, thereby slowing the circuit. Another difference between gate and conventional XOR circuit is how early the pass transistor contribution affects the output. For gate , the pass transistor, such as transistor in the example above, begins contributing almost immediately.
As soon as the input starts changing, the output also starts changing. For the conventional XOR circuit , the early part of the transition is wasted waiting for the gates of the transistors turning on to surpass the threshold. On the other hand, XOR gate has its pass transistor contributing to the output even while the inverter transistor i.
In Fig. The inverting stage comprises a P-type transistor and N-type transistor , in addition to input terminals and XNOR gate also includes an output terminal As shown in Fig. The circuits share input terminals. In the circuit of Fig. However, it's important to note that this behavior differs from the strict definition of exclusive or, which insists that exactly one input must be true for the output to be true. Each of the symbols below can be used to represent an XOR gate.
There are multiple international standards defined, and one may preferred over the other in your region of the world. Multiple-input gates on All About Circuits. Simulate with Logicly Logicly provides an engaging, hands-on learning environment for teaching logic gates and circuits.
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